1. Field of the Invention
The present invention relates to a multilayer chip capacitor, and more particularly, to a multi-terminal multilayer chip capacitor which can efficiently increase equivalent series resistance (ESR) while minimizing an increase in equivalent series inductance (ESL), and is suitable to be used as a decoupling capacitor of a power distribution network of a micro processor unit (MPU).
2. Description of the Related Art
An operating frequency for a high-speed micro processor unit (MPU) is continuously increasing, leading to an increase in current consumption, and an operating voltage for an MPU chip is being lowered. Thus, it becomes more difficult to suppress noise of a DC supply voltage, which occurs due to a sudden fluctuation of a load current of the MPU below a certain level, generally, 5˜10%. A multilayer chip capacitor is being widely used in a power distribution network to remove the voltage noise. The multilayer chip capacitor for decoupling removes voltage noise by supplying a current to a central processing unit (CPU) at the time of the sudden fluctuation of the load current.
The load current fluctuates even more rapidly with the further increase in operating frequency of the MPU. Therefore, a decoupling capacitor is required to have higher capacitance, higher equivalent series resistance (ESR) and lower equivalent series inductance (ESL), so that the magnitude of an impedance of the power distribution network can be maintained at a low and constant level within a broad frequency band. This can ultimately contribute to suppressing the voltage noise caused by the sudden fluctuation of the load current.
In order to achieve low ESL, U.S. Pat. No. 5,880,925 discloses a multilayer capacitor in which external electrodes of positive (+) polarity are alternated with external electrodes of negative (−) polarity on both side faces of a capacitor body, and leads of first and second internal electrodes of opposite polarity are disposed adjacent to each other in an interdigitated arrangement. Accordingly, fluxes caused by high-frequency current flowing in the internal electrodes cancel each other, thereby reducing parasitic inductance of the capacitor. However, the internal electrodes each having four or more leads result in excessively low ESR, which causes a power circuit to be unstable.
U.S. Pat. No. 6,441,459 discloses a method of using only one lead at each internal electrode. Since only one lead is used for each internal electrode, a power circuit is prevented from being unstable due to the excessively low ESR. However, there is a limit in increasing the ESR, using such a small number of leads. For example, in a capacitor proposed by U.S. Pat. No. 6,441,459, leads of internal electrodes adjacent in a stack direction remain in close proximity and thus a current path at the internal electrodes becomes short, which limits the increase in ESR.